This invention relates to programmable logic devices, and more particularly to providing programmable logic devices with content addressable memory capabilities.
Heile U.S. patent application Ser. No. 09/034,050, filed Mar. 3, 1998 (which is hereby incorporated by reference herein in its entirety), shows that programmable logic array integrated circuit devices that have large blocks of random access memory (xe2x80x9cRAMxe2x80x9d) (or read-only memory (xe2x80x9cROMxe2x80x9d)) can be equipped to facilitate the performance of product term (xe2x80x9cp-termxe2x80x9d) logic in the RAM (or ROM). (For convenience herein, the ROM alternative will be understood to be included in references to RAM.) As the immediately above-mentioned reference explains, the ability to perform p-term logic in large blocks of RAM on a programmable logic device that may also include other types of programmable logic capability (e.g., large numbers of small, programmable, look-up tables for performing look-up table logic) increases the flexibility and usability of the device.
There are also applications of programmable logic devices that would benefit from having content addressable memory capability on the devices. A content addressable memory is one in which different xe2x80x9cwordsxe2x80x9d of data are stored in different word locations in the memory, and when data matching one of the stored words is applied to the memory, the memory responds by outputting an indication of the location found to contain the applied data. Content addressable memories (xe2x80x9cCAMsxe2x80x9d) are also sometimes called associative memories.
In view of the foregoing, it is an object of this invention to provide programmable logic devices with improved content addressable memory capabilities.
It is another object of this invention to provide programmable logic devices with content addressable memories, the contents of which can be efficiently changed during operation of the device.
These and other objects of the invention are accomplished in accordance with the principles of the invention by providing programmable logic devices of the type shown in the immediately above-mentioned reference with output circuitry for the RAM blocks that allows the p-term capabilities of the device to be used to provide content addressable memory outputs if content addressable memory operation is desired. In addition, to increase the efficiency with which the contents of a RAM block being used as a content addressable memory can be changed, circuitry is provided for allowing certain read address signals to be applied to certain write address leads of the RAM block, with selective modification of those read address signals. Used in this way, the read address signals control the writing of new data into a selected word location in the RAM block in such a way that fewer write cycles are required to change the contents of a word location. For example, only two write cycles may be required to change a word of any length. If a word may include xe2x80x9cdon""t carexe2x80x9d bits, then three write cycles may be required to change a word of any length.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.